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Research on synchronous parallel coding algorithm of medium length BCH and FPGA implementation

  • Ce Lun Liu
  • , Kai Zhang
  • , Sen Quan Fan
  • , Yan Dong Huang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The error correction capability of BCH is very strong, especially for the short and medium length of codes, which performance reaches the theory value. Besides, it has a strict algebraic structure, which plays an important role in the encode theory. But traditional serial BCH has a low throughput, so it cannot satisfy high speed communication. This paper designed a parallel synchronization encode and decode algorithm, and used FPGA to simulate. Experiment result shows that the proposed algorithm can satisfy the requirement of code rate and hardware resources consumption, so the algorithm has a very useful practical value.

Original languageEnglish (US)
Title of host publicationAdvances in Mechatronics, Automation and Applied Information Technologies
Pages1084-1087
Number of pages4
DOIs
StatePublished - 2014
Externally publishedYes
Event2013 International Conference on Mechatronics and Semiconductor Materials, ICMSCM 2013 - Xi'an, China
Duration: Sep 28 2013Sep 29 2013

Publication series

NameAdvanced Materials Research
Volume846-847
ISSN (Print)1022-6680

Conference

Conference2013 International Conference on Mechatronics and Semiconductor Materials, ICMSCM 2013
Country/TerritoryChina
CityXi'an
Period9/28/139/29/13

Keywords

  • BCH code
  • Parallel codec
  • Sync encoding and decoding

ASJC Scopus subject areas

  • General Engineering

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